1. Field of the Invention
The present invention relates to a semiconductor IC (integrated circuit) device including an internal booster circuit for internally boosting up a power source voltage as supplied from an outer voltage source.
2. Description of the Related Art
An electrically erasable, programmable read only memory (EEPROM) requires a high voltage of, for example, about 20 V for data alteration and erasure of memory cells. A recent EEPROM is designed to internally boost up a power source voltage (usually 5 V) coming from an outer source, not to directly use an external high voltage. Since the user need not prepare any high voltage source, the EEPROM becomes more user-friendly.
FIG. 1 shows a conventional charge pumping circuit which is employed as an internal booster circuit for EEPROM. Between input voltage node IN and booster output node OUT a plurality of N channel enhancement type MOS (insulated gate type) transistors T1 to Tn are cascade-circuited each having its gate connected directly to its drain. A clock signal .phi.1 of a first phase is supplied via capacitor C1 to the node of each of the odd-numbered transistors T1 to Tn, while a clock signal .phi.2 of a second phase is supplied via capacitor C2 to the node of each of the even-numbered transistors. Respective capacitors C1 and C2 have a common capacitive values. As will be appreciated from FIG. 2, the clock signals .phi.1 and .phi.2 are not synchronized with each other and their amplitude level is equal to that of power source voltage V.sub.DD, noting that the power source voltage V.sub.DD is applied to input voltage node IN.
In the internal booster circuit shown in FIG. 1, with the clock signal .phi.1 at a high level, a voltage on node Ni is boosted up to the power source voltage V.sub.DD level when the clock signal .phi.1 is supplied via capacitor C1 to that node. Transistor Ti whose gate is connected to node IN is turned ON and a voltage on a subsequent stage node Ni+1 is boosted up by a level: EQU V.sub.DD -V.sub.TH -Q/C
where:
V.sub.TH : the gate threshold voltage of transistor Ti,
Q: the amount of charge transferred from node Ni to node Ni+1, and
C: the capacitive value of capacitors C1, C2.
With the clock signal .phi.1 at a low level, transistor Ti is turned OFF. When the clock signal .phi.2 goes high, a voltage on a subsequent stage node Ni+1 is boosted up by a level V.sub.DD. That is, upon receipt of the clock signals .phi.1, .phi.2, the booster circuit boosts up a voltage at a rate of EQU V.sub.DD -V.sub.TH -Q/C
per pair of nodes. Through the repetitive charge pumping operation, a predetermined boost-up voltage output emerges on a final booster output node OUT. Since, in practice, the gate threshold voltage Vth of transistor Ti is increased by a back bias effect in the boost-up process, the booster circuit fails to boost up the voltage at a rate of V.sub.DD -V.sub.TH -Q/C =0. FIG. 3 shows a relation between a current output supplied and a boost-up output of the charge pumping circuit. As shown in FIG. 3, a current output supplied becomes very small when the power source voltage V.sub.DD is small.
There is an increasing tendency that EEPROMs will be incorporated into a portable electronic apparatus. A battery power source of about 3 V is usually employed in that application. For a voltage level lower than about 3 V (battery power source), however, the conventional internal booster circuit fails to exhibit an adequate current supply capacity.